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Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
Batten, C. Joshi, A. Orcutt, J. Khilo, A. Moss, B. Holzwarth, C. Popovic, M. Hanqing Li Smith, H. Hoyt, J. Kartner, F. Ram, R. Stojanovic, V. Asanovic, K.
Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA;

This paper appears in: High Performance Interconnects, 2008. HOTI '08. 16th IEEE Symposium on
Publication Date: 26-28 Aug. 2008
On page(s): 21-30
Location: Stanford, CA,
ISSN: 1550-4794
ISBN: 978-0-7695-3380-3
INSPEC Accession Number: 10187063
Digital Object Identifier: 10.1109/HOTI.2008.11
Current Version Published: 2008-09-03

Abstract
We present a new monolithic silicon photonics technology suited for integration with standard bulk CMOS processes, which reduces costs and improves opto-electrical coupling compared to previous approaches. Our technology supports dense wavelength-division multiplexing with dozens of wavelengths per waveguide. Simulation and experimental results reveal an order of magnitude better energy-efficiency than electrical links in the same technology generation. Exploiting key features of our photonics technology, we have developed a processor-memory network architecture for future manycore systems based on an opto-electrical global crossbar. We illustrate the advantages of the proposed network architecture using analytical models and simulations with synthetic traffic patterns. For a power-constrained system with 256 cores connected to 16 DRAM modules using an opto-electrical crossbar, aggregate network throughput can be improved by ap8-10times compared to an optimized purely electrical network.

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