Error floors in LDPC codes: Fast simulation, bounds and hardware emulation
Lee, P.
Dolecek, L.
Zhengya Zhang
Anantharam, V.
Borivoje
Wainwright, M.J.
EECS Dept., Univ. of California, Berkeley, CA;
This paper appears in: Information Theory, 2008. ISIT 2008. IEEE International Symposium on
Publication Date: 6-11 July 2008
On page(s): 444-448
Location: Toronto, ON,
ISBN: 978-1-4244-2256-2
INSPEC Accession Number: 10156351
Digital Object Identifier: 10.1109/ISIT.2008.4595025
Current Version Published: 2008-08-08
Abstract
The error-correcting performance of low-density parity check (LDPC) codes, when decoded using practical iterative decoding algorithms, is known to be very close to Shannon limits in the asymptotic limit of large blocklengths. A substantial limitation to the use of finite-length LDPC codes is the presence of an error floor in the low frame error rate (FER) region. This paper develops two methods, a stochastic one based on importance sampling and a deterministic one based on high SNR asymptotics, as applied to suitably defined absorbing structures within the LDPC code, to predict error floors. Our results are in very close agreement with hardware-based experimental results, and moreover extend the prediction of the error probability to as low as 10-30. Our deterministic estimates are guaranteed to be a lower bound to the error probability in the high SNR regime.
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