Enhanced endurance of dual-bit SONOS NVM cells using the GIDL read method
Padilla, A.
Sunyeong Lee
Carlton, D.
Tsu-Jae King Liu
Dept. of Electr. Eng. & Comput. Sci., Univ. of California at Berkeley, Berkeley, CA;
This paper appears in: VLSI Technology, 2008 Symposium on
Publication Date: 17-19 June 2008
On page(s): 142-143
Location: Honolulu, HI,
ISBN: 978-1-4244-1802-2
INSPEC Accession Number: 10140389
Digital Object Identifier: 10.1109/VLSIT.2008.4588595
Current Version Published: 2008-08-05
Abstract
Gate-induced drain leakage (GIDL) current is demonstrated to be more sensitive to charge stored locally within the gate-dielectric stack, as compared with the transistor threshold voltage (VT). Thus the sensing of GIDL rather than VT is advantageous for dual-bit SONOS NVM cell read operation, not only because it mitigates the complementary-bit disturb (CBD) issue and hence facilitates gate-length scaling, but also because it allows for reductions in stored charge and hence lower program/erase voltages for improved endurance.
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