Large-scale read/write margin measurement in 45nm CMOS SRAM arrays
Zheng Guo
Carlson, A.
Liang-Teck Pang
Duong, K.
Tsu-Jae King Liu
Nikolic, B.
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA;
This paper appears in: VLSI Circuits, 2008 IEEE Symposium on
Publication Date: 18-20 June 2008
On page(s): 42-43
Location: Honolulu, HI,
ISBN: 978-1-4244-1804-6
INSPEC Accession Number: 10153541
Digital Object Identifier: 10.1109/VLSIC.2008.4585944
Current Version Published: 2008-08-01
Abstract
Distributions of read and write noise margins in large CMOS SRAM arrays are investigated by directly measuring the bit-line current during bitline / wordline (write) or cell supply (read) voltage sweep in a 768 Kb 45 nm CMOS SRAM test-chip. Good correlation between write/read margin estimates through the bit-line measurements and the DC read SNM (RSNM) and IW measurements in small on-chip SRAM macros with wired-out storage nodes are demonstrated. Four common writeability metrics are correlated and compared. Array-level characterization of SRAM cell read stability and writeability allow fast and accurate characterization of high-density SRAM arrays is scalable for capturing up to 6 standard deviations of parameter variations.
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