Novel Pseudo-Drain (PD) RF power cell in 0.13 um CMOS technology

This paper proposes a cost-effective RF power cell manufactured in an advanced 0.13 um CMOS technology. Without adding additional masks, cost, and process, the power performance can be improved just by using the standard N-well and shallow-trench-isolation processes to form a higher resistive region. This “Pseudo-Drain” structure increases the breakdown voltage to more than 4.3V and is higher than the value of 2.5V of the standard 0.13 um core-MOS transistor. This transistor exhibits a high f
T
×BV
DS
product of 352 for CMOS power FETs. Cutoff frequency and maximum oscillation frequency of 83 GHz and 124 GHz were achieved at a drain bias of 1.2V, respectively; while the maximum power gain, output power and power-added efficiency were 25.6 dB, 19 dBm, and 55%, respectively. Good RF linearity and noise figure were also obtained, as demonstrated by an OIP3 and NF
min
of 28.32 dBm and 0.4 dB. The presented RF power transistor is cost effective and can be used for power amplifier integration in RF-CMOS SOC.