Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic
Tsung-Te Liu
Alarcon, L.P.
Pierson, M.D.
Rabaey, J.M.
Berkeley Wireless Res. Center, California Univ., Berkeley, CA;
This paper appears in: Asynchronous Circuits and Systems, 2008. ASYNC '08. 14th IEEE International Symposium on
Publication Date: 7-10 April 2008
On page(s): 105-115
Location: Newcastle upon Tyne,
ISSN: 1522-8681
ISBN: 978-0-7695-3107-6
INSPEC Accession Number: 10073902
Digital Object Identifier: 10.1109/ASYNC.2008.23
Current Version Published: 2008-07-09
Abstract
This paper presents the design and implementation of a low energy asynchronous logic architecture using sense amplifier-based pass transistor logic (SAPTL). The SAPTL structure can realize very low energy computation by using low leakage pass transistors and low supply voltage. The introduction of asynchronous operation in SAPTL further improves energy-delay performance and reliability without increasing hardware complexity. We show two different self-timed approaches using a bundled-data and a dual-rail handshaking protocol, respectively. The proposed self-timed SAPTL architectures provide robust and efficient asynchronous computation using a glitch-free protocol to avoid possible dynamic timing hazards. Simulation results show that the self-timed SAPTL with dual-rail protocol exhibits energy-delay characteristics better than synchronous and bundled-data self-timed approaches.
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