Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors
Polian, I.
Reddy, S.M.
Becker, B.
Georges-Kohler-Allee 51, Albert-Ludwigs-Univ., Breisgau;
This paper appears in: Symposium on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual
Publication Date: 7-9 April 2008
On page(s): 257-262
Location: Montpellier,
ISBN: 978-0-7695-3291-2
INSPEC Accession Number: 10117251
Digital Object Identifier: 10.1109/ISVLSI.2008.22
Current Version Published: 2008-07-15
Abstract
Selective hardening aims at achieving maximal soft error rate reduction at reasonable cost by applying hardening techniques to most susceptible circuit nodes only. Logical, electrical and latching-window masking effects must all be considered when calculating the susceptibility of circuit nodes to soft errors. We introduce a scalable selective hardening method based on an approximate calculation of fault detection probabilities at the nodes. Error probability reduction comparable to that obtained by the exact BDD-based algorithm (which is not scalable) can be achieved by setting an over-ambitious optimization target. The run times are negligible even for industrial multiple-million-gates circuits. Existing approaches for calculating electrical and latching-window masking can be readily incorporated into the framework.
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