Selective Hardening in Early Design Steps
Zoellin, C.G.
Wunderlich, H.-J.
Polian, I.
Becker, B.
Stuttgart Univ., Stuttgart;
This paper appears in: European Test, 2008 13th
Publication Date: 25-29 May 2008
On page(s): 185-190
Location: Verbania,
ISSN: 1530-1877
ISBN: 978-0-7695-3150-2
INSPEC Accession Number: 10060330
Digital Object Identifier: 10.1109/ETS.2008.30
Current Version Published: 2008-07-02
Abstract
Hardening a circuit against soft errors should be performed in early design steps before the circuit is laid out. A viable approach to achieve soft error rate (SER) reduction at a reasonable cost is to harden only parts of a circuit. When selecting which locations in the circuit to harden, priority should be given to critical spots for which an error is likely to cause a system malfunction. The criticality of the spots depends on parameters not all available in early design steps. We employ a selection strategy which takes only gate-level information into account and does not use any low-level electrical or timing information. We validate the quality of the solution using an accurate SER estimator based on the new UGC particle strike model. Although only partial information is utilized for hardening, the exact validation shows that the susceptibility of a circuit to soft errors is reduced significantly. The results of the hardening strategy presented are also superior to known purely topological strategies in terms of both hardware overhead and protection.
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