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Numerical Study of Flicker Noise in p-Type $\hbox {Si}_{0.7}\hbox {Ge}_{0.3}/\hbox {Si}$ Heterostructure MOSFETs
Chia-Yu Chen Yang Liu Dutton, R.W. Sato-Iwanaga, J. Inoue, A. Sorada, H.
Center for Integrated Syst., Stanford Univ., Stanford, CA;

This paper appears in: Electron Devices, IEEE Transactions on
Publication Date: July 2008
Volume: 55, Issue: 7
On page(s): 1741-1748
Location: Lausanne, Switzerland,
ISSN: 0018-9383
INSPEC Accession Number: 10064417
Digital Object Identifier: 10.1109/TED.2008.925329
Current Version Published: 2008-06-17

Abstract
Device-level simulation capabilities have been developed to investigate low-frequency noise behavior in p-type Si_0.7Ge_0.3/Si heterostructure MOS (SiGe p-HMOS) transistors. The numerical model is based on the impedance field method; it accounts for a trap-induced carrier number fluctuation, a layer-dependent correlated mobility fluctuation, and a Hooge mobility fluctuation in the buried and parasitic surface channels, respectively. Simulations based on such models have been conducted for SiGe p-HMOS transistors, and the results have been carefully correlated with experimental data. Quantitative agreement has been obtained in terms of the noise level dependence on gate biases, drain currents, and body biases, revealing the important role of the dual channels in the low-frequency noise behavior of SiGe p-HMOS devices.

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