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Avoiding communication in sparse matrix computations
Demmel, J.
Hoemmen, M.
Mohiyuddin, M.
Yelick, K.
Dept. of Electr. Eng. & Comput. Sci., Univ. of California at Berkeley, Berkeley, CA;
This paper appears in: Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on
Publication Date: 14-18 April 2008
On page(s): 1-12
Location: Miami, FL,
ISSN: 1530-2075
ISBN: 978-1-4244-1693-6
INSPEC Accession Number: 10025189
Digital Object Identifier: 10.1109/IPDPS.2008.4536305
Current Version Published: 2008-06-03
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The performance of sparse iterative solvers is typically limited by sparse matrix-vector multiplication, which is itself limited by memory system and network performance. As the gap between computation and communication speed continues to widen, these traditional sparse methods will suffer. In this paper we focus on an alternative building block for sparse iterative solvers, the "matrix powers kernel" [x, Ax, A2x, ..., Akx], and show that by organizing computations around this kernel, we can achieve near-minimal communication costs. We consider communication very broadly as both network communication in parallel code and memory hierarchy access in sequential code. In particular, we introduce a parallel algorithm for which the number of messages (total latency cost) is independent of the power k, and a sequential algorithm, that reduces both the number and volume of accesses, so that it is independent of k in both latency and bandwidth costs. This is part of a larger project to develop "communication-avoiding Krylov subspace methods," which also addresses the numerical issues associated with these methods. Our algorithms work for general sparse matrices that "partition well". We introduce parallel performance models of matrices arising from 2D and 3D problems and show predicted speedups over a conventional algorithm of up to 7times on a petaflop-scale machine and up to 22times on computation across the grid. Analogous sequential performance models of the same problems predict speedups over a conventional algorithm of up to 10times on an out-of-core implementation, and up to 2.5times when we use our ideas to reduce off-chip latency and bandwidth to DRAM. Finally, we validate the model on an out-of-core sequential implementation and measured a speedup of over 3times, which is close to the predicted speedup.
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