Lattice Boltzmann simulation optimization on leading multicore platforms
Williams, S.
Carter, J.
Oliker, L.
Shalf, J.
Yelick, K.
CRD/NERSC, Lawrence Berkeley Nat. Lab., Berkeley, CA;
This paper appears in: Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on
Publication Date: 14-18 April 2008
On page(s): 1-14
Location: Miami, FL,
ISSN: 1530-2075
ISBN: 978-1-4244-1693-6
INSPEC Accession Number: 10025179
Digital Object Identifier: 10.1109/IPDPS.2008.4536295
Current Version Published: 2008-06-03
Abstract
We present an auto-tuning approach to optimize application performance on emerging multicore architectures. The methodology extends the idea of search-based performance optimizations, popular in linear algebra and FFT libraries, to application-specific computational kernels. Our work applies this strategy to a lattice Boltzmann application (LBMHD) that historically has made poor use of scalar microprocessors due to its complex data structures and memory access patterns. We explore one of the broadest sets of multicore architectures in the HPC literature, including the Intel Clovertown, AMD Opteron X2, Sun Niagara!, STI Cell, as well as the single core Intel Itanium.2. Rather than hand-tuning LBMHD for each system, we develop a code generator that allows us identify a highly optimized version for each platform, while amortizing the human programming effort. Results show that our auto- tuned LBMHD application achieves up to a 14times improvement compared with the original code. Additionally, we present detailed analysis of each optimization, which reveal surprising hardware bottlenecks and software challenges for future multicore systems and applications.
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