Automatic Test Pattern Generation for Interconnect Open Defects
Spinner, S.
Polian, I.
Engelke, P.
Becker, B.
Keim, M.
Wu-Tung Cheng
Comput. Archit. Group, Albert-Ludwigs-Univ., Freiburg;
This paper appears in: VLSI Test Symposium, 2008. VTS 2008. 26th IEEE
Publication Date: April 27 2008-May 1 2008
On page(s): 181-186
Location: San Diego, CA,
ISSN: 1093-0167
ISBN: 978-0-7695-3123-6
INSPEC Accession Number: 9964438
Digital Object Identifier: 10.1109/VTS.2008.30
Current Version Published: 2008-05-07
Abstract
We present a fully automated flow to generate test patterns for interconnect open defects. Both inter-layer opens (open- via defects) and arbitrary intra-layer opens can be targeted. An aggressor-victim model used in industry is employed to describe the electrical behavior of the open defect. The flow is implemented using standard commercial tools for parameter extraction (PEX) and test generation (ATPG). A highly optimized branch-and bound algorithm to determine the values to be assigned to the aggressor lines is used to reduce both the ATPG efforts and the number of aborts. The resulting test sets are smaller and achieve a higher defect coverage than stuck-at n-detection test sets, and are robust against process variations.
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