Variability Driven Gate Sizing for Binning Yield Optimization
Davoodi, A.
Srivastava, A.
Dept. of Electr. & Comput. Eng., Univ. of Wisconsin, Madison, WI;
This paper appears in: Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publication Date: June 2008
Volume: 16,
Issue: 6
On page(s): 683-692
Location: San Francisco, CA, USA,
ISSN: 1063-8210
INSPEC Accession Number: 10173366
Digital Object Identifier: 10.1109/TVLSI.2008.2000252
Current Version Published: 2008-05-20
Abstract
High performance applications are highly affected by process variations due to considerable spread in their expected frequencies after fabrication. Typically ldquobinningrdquo is applied to those chips that are not meeting their performance requirement after fabrication. Using binning, such failing chips are sold at a loss (e.g., proportional to the degree that they are failing their performance requirement). This paper discusses a gate-sizing algorithm to minimize ldquoyield-lossrdquo associated with binning. We propose a binning yield-loss function as a suitable objective to be minimized. We show this objective is convex with respect to the size variables and consequently can be optimally and efficiently solved. These contributions are yet made without making any specific assumptions about the sources of variability or how they are modeled. We show computation of the binning yield-loss can be done via any desired statistical static timing analysis (SSTA) tool. The proposed technique is compared with a recently proposed sensitivity-based statistical sizer, a deterministic sizer with worst-case variability estimate, and a deterministic sizer with relaxed area constraint. We show consistent improvement compared to the sensitivity-based approach in quality of solution (final binning yield-loss value) as well as huge run-time gain. Moreover, we show that a deterministic sizer with a relaxed area constraint will also result in reasonably good binning yield-loss values for the extra area overhead.
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