Software-cooperative power-efficient heterogeneous multi-core for media processing
Shikano, H.
Ito, M.
Uchiyama, K.
Odaka, T.
Hayashi, A.
Masuura, T.
Mase, M.
Shirako, J.
Wada, Y.
Kimura, K.
Kasahara, H.
Hitachi Ltd., Tokyo;
This paper appears in: Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific
Publication Date: 21-24 March 2008
On page(s): 736-741
Location: Seoul,
ISBN: 978-1-4244-1921-0
INSPEC Accession Number: 9940584
Digital Object Identifier: 10.1109/ASPDAC.2008.4484049
Current Version Published: 2008-04-08
Abstract
A heterogeneous multi-core processor (HMCP) architecture, which integrates general purpose processors (CPU) and accelerators (ACC) to achieve high-performance as well as low-power consumption with the support of a parallelizing compiler, was developed. The evaluation was performed using an MP3 audio encoder on a simulator that accurately models the HMCP. It showed that 16-frame encoding on the HMCP with four CPUs and four ACCs yielded 24.5-fold speed-up of performance against sequential execution on one CPU. Furthermore, power saving by the compiler reduced energy consumption of the encoding to 0.17 J, namely, by 28.4%.
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