An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors
Dongwan Shin
Gerstlauer, A.
Domer, R.
Gajski, D.D.
Univ. of California, Irvine;
This paper appears in: Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publication Date: April 2008
Volume: 16,
Issue: 4
On page(s): 466-475
Location: San Francisco, CA, USA,
ISSN: 1063-8210
INSPEC Accession Number: 9920548
Digital Object Identifier: 10.1109/TVLSI.2007.915390
Current Version Published: 2008-03-21
Abstract
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of control on RTL design, push-button type synthesis is not accepted by many designers. Interactive design with assistance of algorithms and tools can be more effective if it provides control to the steps of synthesis. In this paper, we propose an interactive RTL design environment which enables designers to control the design steps and to integrate hardware components into a system. Our design environment is targeting a generic RTL processor architecture and supporting pipelining, multicycling, and chaining. Tasks in the RTL design process include clock definition, component allocation, scheduling, binding, and validation. In our interactive environment, the user can control the design process at every stage, observe the effects of design decisions, and manually override synthesis decisions at will. We present a set of experimental results that demonstrate the benefits of our approach. Our combination of automated tools and interactive control by the designer results in quickly generated RTL designs with better performance than fully-automatic results, comparable to fully manually optimized designs.
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