Abstract:
This paper proposes a pipelined, systolic architecture for two-dimensional discrete Fourier transform (DFT) computation which is highly concurrent. The architecture consi...Show MoreMetadata
Abstract:
This paper proposes a pipelined, systolic architecture for two-dimensional discrete Fourier transform (DFT) computation which is highly concurrent. The architecture consists of two, one-dimensional DFT blocks connected via an intermediate buffer. The proposed architecture offers low latency as well as high throughput and can perform both one-and two-dimensional DFTs. The architecture supports transform length that is not power of two and not based on products of co-prime numbers. The simulation and synthesis were carried out using Cadence tools, NcSim and RTL Compiler respectively, with 180 nm libraries.
Date of Conference: 04-06 January 2008
Date Added to IEEE Xplore: 07 February 2008
ISBN Information: