Test cost efficiency exploration for CMT processors
Jia Li
Yu Hu
Xiaowei Li
CAS, Beijing;
This paper appears in: TENCON 2007 - 2007 IEEE Region 10 Conference
Publication Date: Oct. 30 2007-Nov. 2 2007
On page(s): 1-4
Location: Taipei,
ISBN: 978-1-4244-1272-3
INSPEC Accession Number: 9823109
Digital Object Identifier: 10.1109/TENCON.2007.4429148
Current Version Published: 2008-01-14
Abstract
Chip multi-threading (CMT) is an architecture that can achieve overall high performance by exploiting high bandwidth rather than high frequency, thus reduce hardware complexity and power. Test cost of this architecture also can be reduced by efficiently utilizing its communication channel bandwidth during test. Because CMT architectures are designed low-power in nature, its testing should also be conducted under stringent power constraints. This paper discusses these above problems and proposes a cost-efficient test scheme. Experimental results show that our test scheme can achieve very short test time and low test data volume under stringent power constraints with low area overhead.
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