A 60-GHz 90-nm CMOS cascode amplifier with interstage matching
Heydari, B.
Reynaert, P.
Adabi, E.
Bohsali, M.
Afshar, B.
Arbabian, M.A.
Niknejad, A.M.
Univ. of California, Berkeley;
This paper appears in: Microwave Integrated Circuit Conference, 2007. EuMIC 2007. European
Publication Date: 8-10 Oct. 2007
On page(s): 88-91
Location: Munich,
ISBN: 978-2-87487-002-6
INSPEC Accession Number: 9803321
Digital Object Identifier: 10.1109/EMICC.2007.4412654
Current Version Published: 2007-12-26
Abstract
The design of a 60 GHz cascode amplifier in a 90 nm technology is described. The amplifier uses an interstage matching to increase the gain and to provide a better power match between the common-source and the common-gate transistor of the cascode device. Both the common-source and the common-gate transistor make use of an optimized round-table layout, which minimizes all terminal resistances and thus improves the mm-wave performance of the nMOS transistors. A record fmax of 300 GHz is achieved for a 40 mum round-table nMOS in 90 nm CMOS. The cascode amplifier achieves a gain of 7.5 dB at 60 GHz with a DC power consumption of only 6.7 mW. When compared to a shared-junction cascode amplifier or a two-stage common-source cascade amplifier, the presented cascode amplifier is favorable in terms of power gain and DC power consumption
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