Flicker-Noise Impact on Scaling of Mixed-Signal CMOS With HfSiON
Yasuda, Y.
Tsu-Jae King Liu
Chenming Hu
Univ. of California, Berkeley;
This paper appears in: Electron Devices, IEEE Transactions on
Publication Date: Jan. 2008
Volume: 55,
Issue: 1
On page(s): 417-422
Location: Lausanne, Switzerland,
ISSN: 0018-9383
INSPEC Accession Number: 9747374
Digital Object Identifier: 10.1109/TED.2007.910759
Current Version Published: 2007-12-26
Abstract
The flicker noise in MOSFETs with short gate lengths (L < 1 mum) is severely degraded by the presence of a thick high-k gate dielectric layer. The gate length dependence of flicker noise becomes stronger with increasing high-k dielectric thickness - but only for n-FET. To explain these phenomena, a model based on excess traps at the gate edges has been developed. This model explains the flicker-noise dependence on high-k dielectric thickness and gate length and has successfully reproduced the experimental data. Based on the model, the impact of gate-length scaling is evaluated for future mixed-signal ICs using high-k gate-dielectric technology. The deployment of high-k gate dielectric adds another gate-length-scaling limit for analog devices due to the noise consideration.
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