Transactors for parallel hardware and software co-design
Asanovic, K.
Comput. Sci. Div., Univ. of California at Berkeley, Berkeley, CA;
This paper appears in: High Level Design Validation and Test Workshop, 2007. HLVDT 2007. IEEE International
Publication Date: 7-9 Nov. 2007
On page(s): 140-142
Location: Irvine, CA,
ISSN: 1552-6674
ISBN: 978-1-4244-1480-2
INSPEC Accession Number: 10018054
Digital Object Identifier: 10.1109/HLDVT.2007.4392802
Current Version Published: 2007-12-10
Abstract
The use of higher-level design specifications is required for large scale embedded systems, yet these must admit efficient hardware and software implementations. The transactor model separates local computation from global communication, and avoids overspecifying the execution of computations within each unit. The use of guarded atomic commands provides a clean model for concurrent activities that share state within each unit, and supports computations on non-deterministic input streams.
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