Finite Element Analysis of Power Dissipation and Stress in 3-D Stack-Up Geometries

This paper explores thermal issues related to through wafer vias and copper interconnects in 3-D microcircuit wafer stack-ups. ANSYS finite element analysis (FEA) software was used to analyze stress resulting from coefficient of thermal expansion mismatches during processing and operating temperature variations. In addition, optimal cooling methods and the resulting maximum power dissipation were investigated. Initial results on the effect of several geometrical factors suggest an optimal configuration which minimizes stress, material usage, and pressure drop. Further, we find that power dissipation on the order of 80 W will be attainable on a 1 cm
²
, four layer structure.