Across Wafer Critical Dimension Uniformity Enhancement Through Lithography and Etch Process Sequence: Concept, Approach, Modeling, and Experiment
Qiaolin Zhang
Poolla, K.
Spanos, C.J.
Univ. of California, Berkeley;
This paper appears in: Semiconductor Manufacturing, IEEE Transactions on
Publication Date: Nov. 2007
Volume: 20,
Issue: 4
On page(s): 488-505
Location: Tokyo, Japan,
ISSN: 0894-6507
INSPEC Accession Number: 9674106
Digital Object Identifier: 10.1109/TSM.2007.907627
Current Version Published: 2007-11-12
Abstract
Across-wafer gate critical dimension (CD) uniformity impacts chip-to-chip performance variation vis-a-vis speed and power. Performance specification for across-wafer CD uniformity has become increasingly stringent as linewidth decreases to 90 nm and below. This paper presents a novel approach to improve across-wafer gate CD uniformity through the lithography and etch process sequence. The proposed approach is to compensate for upstream and downstream systematic CD variation components in the litho-etch process sequence by optimizing across-wafer post exposure bake (PEB) temperature profiles. More precisely, we first construct a temperature-to-offset model that relates the PEB temperature profiles to the setpoint offsets of multi-zone PEB plates. A second model relating across-wafer CD to setpoint offsets of PEB plates is then identified from CD scanning electron microscope measurements. Post-develop and post-etch CD uniformity enhancement methodologies are then proposed based on the CD-to-offset model and temperature-to-offset models. The temperature-to-offset model is determined to be more appropriate for use in CD uniformity control due to its superior fidelity and portability as compared with the CD-to-offset model. We demonstrate that about 1-nm reduction in standard deviation of post-etch CD variation was achieved in the verification experiment, which validated the efficacy of proposed CD uniformity control approach.
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