Low-Power Successive Approximation Converter With 0.5 V Supply in 90 nm CMOS
Gambini, S.
Rabaey, J.
Univ. of California, Berkeley;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Nov. 2007
Volume: 42,
Issue: 11
On page(s): 2348-2356
Location: Lille, France,
ISSN: 0018-9200
INSPEC Accession Number: 9671182
Digital Object Identifier: 10.1109/JSSC.2007.906210
Current Version Published: 2007-10-22
Abstract
We report on the design and characterization of an ultralow-power converter, designed for use in baseband digitization in wireless sensor network radio receivers. The converter uses a successive approximation architecture and operates robustly with a supply voltage as low as 450 mV, overcoming charge leakage limitations. Implemented in a 90 nm CMOS process, this design achieves a figure of merit of 0.14 pJ/Conv.Step for the converter core and shows the integration of a complete data-conversion subsystem, including reference generation, from a 0.5 V supply.
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