Novel High-Speed Redundant Binary to Binary converter using Prefix Networks

Fast addition and multiplication are of paramount importance in many arithmetic circuits and processors. The use of redundant number system for efficient implementation of these operations has been widely discussed in literature. A redundant binary to binary converter lies directly within the critical path of any operations in this number system, thereby dictating the performance of the overall circuit. In this paper, a new redundant binary to binary converter is proposed using the logic of prefix adders. Though carry propagation is still present in the proposed implementation, the latency has been reduced to O(log n) by the use of sparse- tree networks. The architecture of the proposed converter has been compared (both qualitatively as well as quantitatively) with the existing designs and is shown to achieve an efficiency of 52% in the overall delay and reduction of 36% in power-delay product.