Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM
Kumar, A.
Qin, H.
Ishwar, P.
Rabaey, J.
Ramchandran, K.
EECS, Univ. of California, Berkeley, CA;
This paper appears in: Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Publication Date: 27-30 May 2007
On page(s): 1867-1870
Location: New Orleans, LA,
ISBN: 1-4244-0920-9
INSPEC Accession Number: 9508349
Digital Object Identifier: 10.1109/ISCAS.2007.378279
Current Version Published: 2007-06-25
Abstract
The authors study leakage-power reduction in standby random access memories (SRAMs) during data-retention. An SRAM cell requires a minimum critical supply voltage (DRV) above which it preserves the stored-bit reliably. Due to process-variations, the intra-chip DRV exhibits variation with a distribution having a diminishing tail. In order to minimize leakage power while preserving data reliably, existing low-power design methods use a worst-case standby supply voltage. This worst-case voltage is larger than the highest DRV among all cells in an SRAM. In contrast, the approach uses aggressive voltage reduction and counters the ensuing unreliability by an error-control code based memory architecture. Using this approach, we explore fundamental trade-offs between power reduction and redundancy present in the SRAM. The authors establish fundamental bounds on the power reduction in terms of the DRV-distribution using techniques from information theory and algebraic coding theory. For an experimental test-chip DRV-distribution in the 90nm CMOS technology, the authors show that 49% power reduction with respect to (w.r.t.) the worst-case is a fundamental lower bound while 40% power reduction w.r.t. the worst-case is achievable by using a practical algebraic coding scheme. The authors also study the power reduction as a function of the block-length for low-latency codes since most applications using SRAM are latency constrained. The authors propose a reliable low-power memory architecture based on the Hamming code for the next test-chip implementation with a predicted power reduction of 33% while accounting for coding overheads
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