Verification-Guided Soft Error Resilience
Seshia, S.A.
Wenchao Li
Mitra, S.
California Univ., Berkeley, CA;
This paper appears in: Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
Publication Date: 16-20 April 2007
On page(s): 1-6
Location: Nice,
ISBN: 978-3-9810801-2-4
INSPEC Accession Number: 9486431
Digital Object Identifier: 10.1109/DATE.2007.364501
Current Version Published: 2007-05-29
Abstract
Algorithmic techniques for formal verification can be used not just for bug-finding, but also to estimate vulnerability to reliability problems and to reduce overheads of circuit mechanisms for error resilience. We demonstrate this idea of verification-guided error resilience in the context of soft errors in latches. We show how model checking can be used to identify latches in a circuit that must be protected in order that the circuit satisfies a formal specification. Experimental results on a Verilog implementation of the ESA SpaceWire communication protocol indicate that the power overhead of soft error protection can be reduced by a factor of 4.35 by using our approach rather than protecting all latches
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