A 1.5MS/s 6-bit ADC with 0.5V supply
Gambini, S.
Rabaey, J.
Univ. of California at Berkeley, Berkeley;
This paper appears in: Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian
Publication Date: 13-15 Nov. 2006
On page(s): 47-50
Location: Hangzhou,
ISBN: 0-7803-97374-7
INSPEC Accession Number: 9664869
Digital Object Identifier: 10.1109/ASSCC.2006.357848
Current Version Published: 2007-05-07
Abstract
A moderate resolution analog-to-digital converter targeting wireless sensor networks applications is presented. Employing a successive approximation architecture, the device achieves 6 bits of resolution at 1.5 MS/s output rate, while drawing 28muA from a low 0.5 V supply, corresponding to a Figure of Merit (FOM) of .25pJ/conversion step. Low-density metal5-metal6 capacitors guarantee feedback DAC linearity while minimizing input capacitance, while the use of a passive sample and hold, combined with a class-AB comparator reduce analog power dissipation to 4muW (30% of the total). The analog core is operational for supply values as low as .3V, even though sampling rate is reduced to 175kS/s.
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