Efficient Modulo (2k±1) Binary to Residue Converters

In this paper, the design of a binary to residue converter architecture based on {2
^k
-1, 2
_k
2
^k
+l} modulo set is presented. New highly-parallel schemes using (p,2) compressors are described for computing the integer modulo operation (X mod m), where m is restricted to the values 2
^k
plusmn1, for any value of k>1 and X is a 16-bit or a 32-bit number For efficient design, novel 3-2, 4-2 and 5-2 compressors are illustrated and are used as the basic building blocks for the proposed converter designs. The resulting circuits are compared, both qualitatively and quantitatively, in standard CMOS cell technology, with the existing circuits. The results show that the proposed architectures are faster and use lesser hardware than similar circuits known making them a viable option for efficient design