Multi-Dimensional Circuit and Micro-Architecture Level Optimization
Zhenyu Qi
Ziegler, M.
Kosonocky, S.V.
Rabaey, J.M.
Stan, M.R.
Dept. of ECE, Virginia Univ., Charlottesville, VA;
This paper appears in: Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on
Publication Date: 26-28 March 2007
On page(s): 275-280
Location: San Jose, CA,
ISBN: 0-7695-2795-7
INSPEC Accession Number: 9475584
Digital Object Identifier: 10.1109/ISQED.2007.105
Current Version Published: 2007-04-10
Abstract
This paper studies multi-dimensional optimization at both circuit and micro-architecture levels. By formulating and solving the optimization problem with conflicting design objectives and multiple tunable knobs, it is revealed that the 'sensitivity balance' strategy proposed in recent works for performance-energy optimization is a special case of a general multi-dimensional optimization framework. The results derived in this paper help the understanding of efficient trade-off among multiple design objectives with multiple knobs. The example of an industrial control logic implemented in PLA shows 22% energy saving and 70% area reduction at the expense of 4% delay increase
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
Cart
