Power and Area Minimization for Multidimensional Signal Processing
Markovic, D.
Nikolic, B.
Brodersen, R.W.
Dept. of Electr. Eng., California Univ., Los Angeles, CA;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: April 2007
Volume: 42,
Issue: 4
On page(s): 922-934
Location: Lille, France,
ISSN: 0018-9200
INSPEC Accession Number: 9381841
Digital Object Identifier: 10.1109/JSSC.2007.892191
Current Version Published: 2007-03-26
Abstract
Sensitivity-based methodology is applied to optimization of performance, power and area across several levels of design abstraction for a complex wireless baseband signal processing algorithm. The design framework is based on a unified, block-based graphical description of the algorithm to avoid design re-entry in various phases of chip development. The use of architectural techniques for minimization of power and area for complex signal processing algorithms is demonstrated using this framework. As a proof of concept, an ASIC realization of the MIMO baseband signal processing for a multi-antenna WLAN is described. The chip implements a 4times4 adaptive singular value decomposition (SVD) algorithm with combined power and area minimization achieving a power efficiency of 2.1 GOPS/mW (12-bit add equivalent) in just 3.5 mm 2 in a standard 90 nm CMOS process. The computational throughput of 70 GOPS is implemented with 0.5 M cells at a 100 MHz clock and 385 mV supply, dissipating 34 mW of power. With optimal channel conditions the algorithm implemented can deliver up to 250 Mb/s over 16 sub-carriers
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
Cart
