Probabilistic CMOS Technology: A Survey and Future Directions

Highly scaled CMOS devices in the nanoscale regime would inevitably exhibit statistical or probabilistic behavior. Such behavior is due to process variations and other perturbations such as noise. Therefore current circuit design methodologies, which depend on the existence of deterministic and uniform devices with no consideration for either power consumption or probabilistic behavior, would no longer be sufficient to design robust circuits. To help overcome this challenge, we have been characterizing CMOS devices with probabilistic behavior (probabilistic CMOS or PCMOS devices) at several levels: from foundational principles to analytical modeling, simulation, fabrication and measurement, as well as innovative approaches to harnessing PCMOS devices in system-on-a-chip architectures which can implement a wide range of applications. In this paper, we present a broad overview of our contributions in the domain of PCMOS, and outline ongoing work and future challenges in this area.