Probabilistic CMOS Technology: A Survey and Future Directions
Akgul, B.E.S.
Chakrapani, L.N.
Korkmaz, P.
Palem, K.V.
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA;
This paper appears in: Very Large Scale Integration, 2006 IFIP International Conference on
Publication Date: 16-18 Oct. 2006
On page(s): 1-6
Location: Nice,
ISBN: 3-901882-19-7
INSPEC Accession Number: 9462231
Digital Object Identifier: 10.1109/VLSISOC.2006.313282
Current Version Published: 2007-02-20
Abstract
Highly scaled CMOS devices in the nanoscale regime would inevitably exhibit statistical or probabilistic behavior. Such behavior is due to process variations and other perturbations such as noise. Therefore current circuit design methodologies, which depend on the existence of deterministic and uniform devices with no consideration for either power consumption or probabilistic behavior, would no longer be sufficient to design robust circuits. To help overcome this challenge, CMOS devices have been characterized with probabilistic behavior (probabilistic CMOS or PCMOS devices) at several levels: from foundational principles to analytical modeling, simulation, fabrication and measurement, as well as innovative approaches to harnessing PCMOS devices in system-on-a-chip architectures which can implement a wide range of applications. This paper presents a broad overview of our contributions in the domain of PCMOS, and outline ongoing work and future challenges in this area
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