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Measurements and analysis of process variability in 90nm CMOS
Nikolic, B. Liang-Teck Pang
Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA;

This paper appears in: Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Publication Date: 23-26 Oct. 2006
On page(s): 505-508
Location: Shanghai,
ISBN: 1-4244-0160-7
INSPEC Accession Number: 9408458
Digital Object Identifier: 10.1109/ICSICT.2006.306337
Current Version Published: 2007-04-02

Abstract
Process variability in deeply scaled CMOS has both random and systematic components, with a varying degree of spatial correlation. A test chip has been built to study the effects of circuit layout on variability of delay and power dissipation in 90nm CMOS. The delay is characterized through the spread of ring oscillator frequencies and the transistor leakage is measured by using an on-chip ADC

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