Source/Drain Extension Region Engineering in Nanoscale Double Gate MOSFETs for Low-Voltage Analog Applications

A novel design methodology to simultaneously improve A
_vo
and f
_T
for low-voltage/low-power analog applications was proposed for the first time using symmetric/asymmetric SDE regions. A significant improvement of about 50% in voltage gain and 85% in cut-off frequency can be achieved by optimally engineered SDE regions as compared to devices with abrupt source/drain regions. The present work provides new opportunities for realizing future low-voltage analog circuits with nanoscale SDE engineered DG MOSFETs