FinFET SRAM with Enhanced Read / Write Margins
Carlson, A.
Guo, Z.
Balasubramanian, S.
Pang, L.T.
King Liu, T.J.
Nikolic, B.
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA;
This paper appears in: International SOI Conference, 2006 IEEE
Publication Date: 2-5 Oct. 2006
On page(s): 105-106
Location: Niagara Falls, NY,
ISSN: 1078-621X
ISBN: 1-4244-0289-1
INSPEC Accession Number: 9220737
Digital Object Identifier: 10.1109/SOI.2006.284456
Current Version Published: 2007-01-15
Abstract
In this work, the impact of this pass-gate feedback (PGFB) technique on cell write-ability is examined, and gate workfunction (Phim) tuning for optimization of the trade-off with read margin is discussed. To further improve cell write-ability, the p-channel pull-up devices can also be operated in BG mode, with their back gates driven by a separate write word line. This pull-up write gating (PUWG) technique is effective for maintaining larger than 6 standard deviations yield down to 0.4V VDD without area penalty, making FinFET-based 6-T SRAM compelling for high-density memory applications
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