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Theory of Fermi Level Pinning of High-k Dielectrics
Shiraishi, K.   Takeuchi, H.   Akasaka, Y.   Watanabe, H.   Umezawa, N.   Chikyow, T.   Nara, Y.   Yamada, K.   Tsu-Jae King Liu  
Graduate Sch. of Pure & Appl. Phys., Tsukuba Univ., Ibaraki;

This paper appears in: Simulation of Semiconductor Processes and Devices, 2006 International Conference on
Publication Date: 6-8 Sept. 2006
On page(s): 306-313
Location: Monterey, CA,
ISBN: 1-4244-0404-5
INSPEC Accession Number: 9431682
Digital Object Identifier: 10.1109/SISPAD.2006.282897
Current Version Published: 2007-01-15

Abstract
Fermi-level pinning of poly-Si and metal-silicide gate materials on Hf-based gate dielectrics has been systematically studied theoretically. Fermi-level pinning in high-work-function materials is governed by the O vacancy generation and subsequent formation of interface dipoles near gate electrodes due to the electron transfer. On the other hand, O interstitial formation plays a crucial role for Fermi-level pinning in low-work-function materials. From our theoretical considerations, we have found that the work-function pinning-free-region generally appears due the difference in the mechanism of Fermi-level pinning of high- and low-work-function materials. The widening of this work-function pinning-free-region is the key issue for the fundamental relaxation of Fermi-level pinning in high-k gate dielectric

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