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Numerical Investigation of Low Frequency Noise in MOSFETs with High-k Gate Stacks
Liu, Y.   Cao, S.   Dutton, R.W.  
Center for Integrated Syst., Stanford Univ., CA;

This paper appears in: Simulation of Semiconductor Processes and Devices, 2006 International Conference on
Publication Date: 6-8 Sept. 2006
On page(s): 99-102
Location: Monterey, CA,
ISBN: 1-4244-0404-5
INSPEC Accession Number: 9431632
Digital Object Identifier: 10.1109/SISPAD.2006.282847
Current Version Published: 2007-01-15

Abstract
Two numerical models based on the impedance field method have been implemented to investigate the flicker noise in MOSFETs with high-kappa gate stacks. The equivalent model uses approximate channel current noise source, while the physical model is based on the Langevin approach and accounts for the non-local carrier tunneling. The scaling impact on the flicker noise is investigated with the developed models. The validity of the models in the sub-threshold regime is examined. Comparison with experimental data indicates the importance of modeling the nonuniform trap energy distribution. The degradation of the flicker noise performance due to halo doping is also studied

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