Advanced Unbounded Model Checking Based on AIGs, BDD Sweeping, And Quantifier Scheduling
Florian Pigorsch
Christoph Scholl
Stefan Disch
Inst. fur Informatik, Albert-Ludwigs-Univ. Freiburg;
This paper appears in: Formal Methods in Computer Aided Design, 2006. FMCAD '06
Publication Date: Nov. 2006
On page(s): 89-96
Location: San Jose, CA,
ISBN: 0-7695-2707-8
INSPEC Accession Number: 9297076
Digital Object Identifier: 10.1109/FMCAD.2006.4
Current Version Published: 2006-12-11
Abstract
In this paper we present a complete method for verifying properties expressed in the temporal logic CTL. In contrast to the majority of verification methods presented in previous years, we support unbounded model checking based on symbolic representations of characteristic functions. Among others, our method is based on an advanced and-inverter graph (AIG) implementation, quantifier scheduling, and BDD sweeping. For several examples, our method outperforms BDD based symbolic model checking by orders of magnitude. However, our approach is also able to produce competitive results for cases where BDD are known to perform well
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