Use of short-loop electrical measurements for yield improvement
Crid Yu
Tinaung Maung
Spanos, C.J.
Boning, D.S.
Chung, J.E.
Hua-Yu Liu
Keh-Jeng Chang
Bartelink, D.J.
California Univ., Berkeley, CA;
This paper appears in: Semiconductor Manufacturing, IEEE Transactions on
Publication Date: May 1995
Volume: 8,
Issue: 2
On page(s): 150-159
ISSN: 0894-6507
References Cited: 8
CODEN: ITSMED
INSPEC Accession Number: 4965187
Digital Object Identifier: 10.1109/66.382279
Current Version Published: 2002-08-06
Abstract
Modern submicron processes are more sensitive to both random and
systematic wafer-level process variation than ever before. Given the
dimensional control limitations of new technologies, the amount of
wafer-to-wafer and within wafer nonuniformity of many steps is becoming
a significant fraction of the total error budget, which already includes
the usual step-to-step allocations. However, a significant portion of
the total observed variability is systematic in nature. Accordingly,
particle defects may not continue to dominate parametric yield loss
without improved understanding of parametric variations. In this paper,
we demonstrate the use of short-loop electrical metrology to carefully
characterize and decouple wafer-level variability of several critical
processing steps. More specifically, we present our method and give
results obtained from variability analyses for lithography critical
dimension (CD) and inter-level dielectric (ILD) thickness control. Using
statistically designed experiments and dedicated test structures, the
main factors affecting dielectric thickness variability has been
identified. The systematic variability from a wafer stepper has been
extracted using a physically based statistical data filter. Once
isolated, the deterministic variability can be modeled and controlled to
enhance process and circuit design for manufacturability (DFM). We hope
that in the future this work will be coupled with novel DFM-oriented CAD
tools that encapsulate this information in a fashion that makes it
useful to process and circuit designers
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