A 10-bit, 20-MS/s, 35-mW pipeline A/D converter
Cho, T.B.
Gray, P.R.
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA;
This paper appears in: Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Publication Date: 1-4 May 1994
On page(s): 499-502
Meeting Date: 05/01/1994 - 05/04/1994
Location: San Diego, CA, USA
ISBN: 0-7803-1886-2
References Cited: 5
INSPEC Accession Number: 4916221
Digital Object Identifier: 10.1109/CICC.1994.379674
Current Version Published: 2002-08-06
Abstract
This paper describes a 10-bit 20-MS/s pipeline A/D converter
implemented in 1.2-μm CMOS technology which achieves a power
dissipation of 35 mW at full speed operation. Circuit techniques used to
achieve this level of power dissipation include operation on a 3.3 V
power supply, optimum scaling of capacitor values through the pipeline,
and digital correction to allow the use of dynamic comparators. Measured
performance includes 0.6 LSB of INL, 59.1 dB of SNDR for 100 kHz input
at 20 MS/s. At Nyquist sampling (10 MHz input), SNDR is 55.0 dB
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