A supercomputer for neural computation
Asanovic, K.
Beck, J.
Feldman, J.
Morgan, N.
Wawrzynek, J.
Int. Comput. Sci. Inst., California Univ., Berkeley, CA;
Abstract
The requirement to train large neural networks quickly has
prompted the design of a new massively parallel supercomputer using
custom VLSI. This design features 128 processing nodes, communicating
over a mesh network connected directly to the processor chip. Studies
show peak performance in the range of 160 billion arithmetic operations
per second. This paper presents the case for custom hardware that
combines neural network-specific features with a general programmable
machine architecture, and briefly describes the design in progress
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