A method for modeling the manufacturability of IC designs
Boskin, E.D.
Spanos, C.J.
Korsh, G.J.
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA;
This paper appears in: Semiconductor Manufacturing, IEEE Transactions on
Publication Date: Aug 1994
Volume: 7,
Issue: 3
On page(s): 298-305
ISSN: 0894-6507
References Cited: 27
CODEN: ITSMED
INSPEC Accession Number: 4775858
Digital Object Identifier: 10.1109/66.311333
Current Version Published: 2002-08-06
Abstract
A methodology for modeling the manufacturability of MOS circuits
has been developed. The fabrication line is described using a small set
of measurable process parameters, whose variation explains the range of
circuit performance seen during production. These same parameters form
the basis of a statistical MOSFET model which combines physical
measurements, global optimization, and regression modeling of key
fitting parameters to accurately predict transistor characteristics over
a wide range of process variation. The fabrication line description in
conjunction with the MOSFET model was used to develop a manufacturing
application, specifically, a performance prediction model which uses the
process parameters as measured on the manufacturing floor to predict the
performance of fabricated integrated circuits before packaging and final
test. The MOSFET model and the performance prediction model are
integrated, and data taken from the manufacturing line can be used to
verify the models, to identify process shifts, and suggest design
improvements for further manufacturability enhancements. The method was
successfully applied to an industrial 1.5-μm CMOS process, and models
were developed and tested for a 1-Mbit EPROM
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
Cart
