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Algorithms for interface timing verification
McMillan, K.L. Dill, D.L.
Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA;

This paper appears in: Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings., IEEE 1992 International Conference on
Publication Date: 11-14 Oct 1992
On page(s): 48-51
Meeting Date: 10/11/1992 - 10/14/1992
Location: Cambridge, MA, USA
ISBN: 0-8186-3110-4
References Cited: 7
INSPEC Accession Number: 4483002
Digital Object Identifier: 10.1109/ICCD.1992.276208
Current Version Published: 2002-08-06

Abstract
Algorithms for analyzing systems of inequalities with min/max constraints that arise in interface timing specifications are examined. A general form of the inequality is shown to be NP-complete, but some interesting special cases can be solved efficiently. A branch-and-bound solution to the general case is developed and applied to a previously published example

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