Suppression of Gate Oscillation of Power MOSFET with Bridge Topology

In order to suppress the oscillation of gate drive signal of the power MOSFET, a equivalent circuit model of the half-bridge inverter considering stray parameters of the drive circuit is put forward based on the equivalent model of the power MOSFET considering junction capacitances, based on which it is known that the oscillation is caused by the high dv/dt produced during the power MOSFET switching and junction capacitances and distributed inductance. The drive circuit parameters are devised optimally according to the transient timing domain three-dimensional curves of parameters corresponding to the oscillation. The oscillation is suppressed obviously through increasing turn-on time of the power MOSFET, and experimental results are given. Both the theoretic analysis and experimental results indicate that the improved circuit can meet the power MOSFET drive requirement perfectly.