A parallel ASIC VLSI neurocomputer for a large number of neurons and billion connections per second speed

A programmable high-performance and high-speed neurocomputer for a large neural network is developed using an application specific IC (ASIC) neurocomputing chip made by CMOS VLSI technology. The neurocomputer consists of one master node and multiple slave nodes which are connected by two data paths, a broadcast bus and a ring bus. The neurocomputer was built on one printed circuit board having 50 VLSI chips that offers 1-2 billion connections/s. This computer uses SIMD (single-instruction multiple-data stream) to simplify hardware and operation, and to ease programming. Only the master node has a program counter that controls both master and slave instructions. The same slave instructions are fed to all slave nodes simultaneously. It can execute complicated computations, memory access and memory address control, and data paths control in a single instruction and in a single time step using a pipeline. The neurocomputer processes forward and backward calculation of multilayer perceptron type neural networks, feedback type neural networks, and any other type of programming.<>