Synthesized Compact Models and Experimental Verifications for Substrate Noise Coupling in Mixed-Signal ICs
Lan, H.
Tze Wee Chen
Chi On Chui
Nikaeen, P.
Jae Wook Kim
Dutton, R.W.
Dept. of Electr. Eng., Stanford Univ., CA;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Aug. 2006
Volume: 41,
Issue: 8
On page(s): 1817-1829
Location: Lille, France,
ISSN: 0018-9200
INSPEC Accession Number: 9010783
Digital Object Identifier: 10.1109/JSSC.2006.877272
Current Version Published: 2006-07-24
Abstract
A synthesized compact modeling (SCM) approach for substrate coupling analysis is presented. The SCM is formulated using a scalable Z matrix approach for heavily doped substrates with a lightly doped epitaxial layer and using a nodal lumped resistance approach for lightly doped substrates. The SCM models require a set of process-dependent fitting coefficients and incorporate geometrical parameters of the substrate ports in a compact form that includes size, perimeter, and separation defined using the geometric mean distance to accommodate both far-field and near-field effects. The SCM approach is verified based on measurement data from two test chips, one in a custom lightly doped process and the other one using a 0.18-mum BiCMOS lightly doped foundry process. The model accuracy is shown to be within 15% compared to measured data extracted from the test patterns. The SCM is exploited with application examples to show substrate model generation efficiency and accuracy at different levels of complexity, including a full chip substrate noise distribution analysis for a 2 mm by 2 mm chip with 319 substrate contacts
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