High-performance, Dependable Multiprocessor
Ramos, J.
Samson, J.
Lupia, D.
Troxel, I.
Subramaniyan, R.
Jacobs, A.
Greco, J.
Cieslewski, G.
Curreri, J.
Fischer, M.
Grobelny, E.
George, A.
Aggarwal, V.
Patel, M.
Some, R.
Honeywell Aerosp., Defense & Space, Clearwater, FL;
This paper appears in: Aerospace Conference, 2006 IEEE
Publication Date: 0-0 0
On page(s): 13 pp.-
Location: Big Sky, MT,
ISBN: 0-7803-9545-X
INSPEC Accession Number: 9110030
Digital Object Identifier: 10.1109/AERO.2006.1655959
Current Version Published: 2006-07-24
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With the ever-increasing demand for higher bandwidth and processing capacity of today's space exploration, space science, and defense missions, the ability to efficiently apply commercial-off-the-shelf (COTS) processors for on-board computing is now a critical need. In response to this need, NASA's new millennium program office has commissioned the development of Dependable Multiprocessor (DM) technology for use in payload and robotic missions. The Dependable Multiprocessor technology is a COTS-based, power-efficient, high-performance, highly dependable, fault-tolerant cluster computer. To date, Honeywell has successfully demonstrated a TRL4 prototype of the Dependable Multiprocessor (Ramos et al., 2005), and is now working on the development of a TRL5 prototype. For the present effort Honeywell has teamed up with the University of Florida via its high-performance computing and simulation (HCS) research laboratory, and together the team has demonstrated major elements of the Dependable Multiprocessor TRL5 system. This paper provides a detailed description of the basic Dependable Multiprocessor technology, and the TRL5 technology prototype currently under development
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