On-Chip Interconnect Networks at the End of the Roadmap: Limits and Nanotechnology Opportunities
Naeemi, A.
barvan, A.
Memdl, J.D.
Georgia Inst. of Technol., Atlanta, GA;
This paper appears in: Interconnect Technology Conference, 2006 International
Publication Date: 0-0 0
On page(s): 201-203
Location: Burlingame, CA,
ISBN: 1-4244-0104-6
INSPEC Accession Number: 9088855
Digital Object Identifier: 10.1109/IITC.2006.1648693
Current Version Published: 2006-07-05
Abstract
Physical models are presented for single- and multi-wall carbon nanotubes. The models are used to quantify the performance enhancements that they can potentially offer if used as interconnects in GSI chips. For short lengths, mono-layer SWCN interconnects can lower capacitance by 50% whereas for long lengths SWCN-bundles can improve conductivity up to 100%. Conductivity of MWCNs increases with diameter if they are longer than a critical length of about 7 mum and decreases otherwise
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