Modeling of charge trapping induced threshold-voltage instability in high-κ gate dielectric FETs
Yang Liu
Shanware, A.
Colombo, L.
Dutton, R.
Center for Integrated Syst., Stanford Univ., CA, USA;
This paper appears in: Electron Device Letters, IEEE
Publication Date: June 2006
Volume: 27,
Issue: 6
On page(s): 489- 491
ISSN: 0741-3106
INSPEC Accession Number: 8935350
Digital Object Identifier: 10.1109/LED.2006.874760
Current Version Published: 2006-05-30
Abstract
The authors have developed a distributed tunneling model to investigate the threshold-voltage instability induced by charge trapping in field-effect transistors (FETs) using high-κ gate dielectric materials. The charge trapping dynamics in the high-κ layer are modeled based on a rate equation, which is self-consistently incorporated into device-level simulations. The model is used to simulate pulsed operation of HfO2 based n-type FETs; good agreement is obtained with pulsed measurements including the dependence of the threshold-voltage shift on pulse heights and durations. The trap-energy-level shift due to the polaron effect is found to be critical to model the pulse-height dependence of the threshold-voltage shift.
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