MOSFET design for forward body biasing scheme
Hokazono, A.
Balasubramanian, S.
Ishimaru, K.
Ishiuchi, H.
Tsu-Jae King Liu
Chenming Hu
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA;
This paper appears in: Electron Device Letters, IEEE
Publication Date: May 2006
Volume: 27,
Issue: 5
On page(s): 387- 389
ISSN: 0741-3106
INSPEC Accession Number: 8888720
Digital Object Identifier: 10.1109/LED.2006.873382
Current Version Published: 2006-05-01
Abstract
Forward body biasing is a solution for continued scaling of bulk-Si CMOS technology. In this letter, the dependence of 30-nm-gate MOSFET performance on body bias is experimentally evaluated for devices with various channel-doping profiles to provide guidance for channel engineering in a forward body-biasing scheme. Furthermore, simulations of 10-nm-gate CMOS (hp22-nm node) devices are performed to study the optimal channel-doping profile and gate work function engineering for a forward biasing scheme.
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