Scaling, power, and the future of CMOS
Horowitz, M.
Alon, E.
Patil, D.
Naffziger, S.
Rajesh Kumar
Bernstein, K.
Stanford Univ., CA;
This paper appears in: Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Publication Date: 5-5 Dec. 2005
On page(s): 7 pp.-15
Location: Washington, DC,
ISBN: 0-7803-9268-x
INSPEC Accession Number: 9060428
Digital Object Identifier: 10.1109/IEDM.2005.1609253
Current Version Published: 2006-04-03
Abstract
This paper briefly reviews the forces that caused the power problem, the solutions that were applied, and what the solutions tell us about the problem. As systems became more power constrained, optimizing the power became more critical; viewing power reduction from an optimization perspective provides valuable insights. Section III describes these insights in more detail, including why Vdd and Vth have stopped scaling. Section IV describes some of the low power techniques that have been used in the past in the context of the optimization framework. This framework also makes it easy to see the impact of variability, which is discussed in more detail in section V along with the adaptive mechanisms that have been proposed and deployed to minimize the energy cost. Section VI describes possible strategies for dealing with the slowdown in gate energy scaling, and the final section concludes by discussing the implications of these strategies for device designers
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